With the further development of computers and communication technologies, a large amount of new-generation input/output (I/O) interfaces emerge, for example, I/O interfaces using gigabit Ethernet (GE) and 10 gigabit Ethernet (10 GE) technologies, and 4G/8G fibre channel (FC) technologies. Rates of I/O interfaces are significantly improved. A bandwidth of a conventional peripheral component interconnect (PCI) bus is no longer capable of coping with a requirement for massive high-bandwidth concurrent reading and writing in a computer system, and the PCI bus becomes a bottleneck in improving system performance. Therefore, a PCIE bus is developed. The PCIE bus is capable of providing an extremely high bandwidth through multiple channels (X1/X2/X4/X8/X16/X32) to satisfy a system requirement.
The PCIE uses a point-to-point communication mode. A tree network structure is formed from a root complex (RC) to endpoint devices (EP). Data exchange in a transmission layer is performed based on a transaction layer packet (TLP). When the PCIE is used as a bus in a board, the simple tree structure is capable of ensuring reliability of the system. When the PCIE bus fails, an impact is limited inside the board. With the change of the computer, network and storage architecture, an advantage of using the PCIE as a switching network among these components becomes prominent. As shown in FIG. 1, a graphics process unit (GPU), a converge network adaptor (CNA), a solid-state disk (SSD), a video acceleration component, and so on provide a virtualization technology, and resource sharing of the GPU, CNA, SSD, and so on may be implemented between central process units (CPU) or between virtual machines (VM) through PCIE switching, thereby improving a utilization ratio of system resources. When the GPU/CNA/SSD/video acceleration component/PCIE switching component or PCIE link fails, abnormities may be caused for all CPUs due to the tree switching structure defined in PCIE specifications, thereby dramatically reducing the reliability of the system.
According to the foregoing description, due to the current tree-structure networking manner of the PCIE, the reliability of the system fails to meet an application requirement.